EC-GSM-IoT Network Synchronization with Support for Large Frequency Offsets

EDGE-based EC-GSM-IoT is a promising candidate for the billion-device cellular IoT (cIoT), providing similar coverage and battery life as NB-IoT. The goal of 20 dB coverage extension compared to EDGE poses significant challenges for the initial network synchronization, which has to be performed well below the thermal noise floor, down to an SNR of -8.5 dB. We present a low-complexity synchronization algorithm supporting up to 50 kHz initial frequency offset, thus enabling the use of a low-cost +/-25 ppm oscillator. The proposed algorithm does not only fulfill the 3GPP requirements, but surpasses them by 3 dB, enabling communication with an SNR of -11.5 dB or a maximum coupling loss of up to 170.5 dB.Comment: Wireless Communications and Networking Conference (WCNC), 201

Do genetic factors protect for early onset lung cancer? A case control study before the age of 50 years

<p>Abstract</p> <p>Background</p> <p>Early onset lung cancer shows some familial aggregation, pointing to a genetic predisposition. This study was set up to investigate the role of candidate genes in the susceptibility to lung cancer patients younger than 51 years at diagnosis.</p> <p>Methods</p> <p>246 patients with a primary, histologically or cytologically confirmed neoplasm, recruited from 2000 to 2003 in major lung clinics across Germany, were matched to 223 unrelated healthy controls. 11 single nucleotide polymorphisms of genes with reported associations to lung cancer have been genotyped.</p> <p>Results</p> <p>Genetic associations or gene-smoking interactions was found for <it>GPX1(Pro200Leu) </it>and <it>EPHX1(His113Tyr)</it>. Carriers of the Leu-allele of <it>GPX1(Pro200Leu) </it>showed a significant risk reduction of OR = 0.6 (95% CI: 0.4–0.8, p = 0.002) in general and of OR = 0.3 (95% CI:0.1–0.8, p = 0.012) within heavy smokers. We could also find a risk decreasing genetic effect for His-carriers of <it>EPHX1(His113Tyr) </it>for moderate smokers (OR = 0.2, 95% CI:0.1–0.7, p = 0.012). Considered both variants together, a monotone decrease of the OR was found for smokers (OR of 0.20; 95% CI: 0.07–0.60) for each protective allele.</p> <p>Conclusion</p> <p>Smoking is the most important risk factor for young lung cancer patients. However, this study provides some support for the T-Allel of <it>GPX1(Pro200Leu) </it>and the C-Allele of <it>EPHX1(His113Tyr) </it>to play a protective role in early onset lung cancer susceptibility.</p

Prevalence of Age-Related Macular Degeneration in Europe: The Past and the Future

Purpose Age-related macular degeneration (AMD) is a frequent, complex disorder in elderly of European ancestry. Risk profiles and treatment options have changed considerably over the years, which may have affected disease prevalence and outcome. We determined the prevalence of early and late AMD in Europe from 1990 to 2013 using the European Eye Epidemiology (E3) consortium, and made projections for the future. Design Meta-analysis of prevalence data. Participants A total of 42 080 individuals 40 years of age and older participating in 14 population-based cohorts from 10 countries in Europe. Methods AMD was diagnosed based on fundus photographs using the Rotterdam Classification. Prevalence of early and late AMD was calculated using random-effects meta-analysis stratified for age, birth cohort, gender, geographic region, and time period of the study. Best-corrected visual acuity (BCVA) was compared between late AMD subtypes; geographic atrophy (GA) and choroidal neovascularization (CNV). Main Outcome Measures Prevalence of early and late AMD, BCVA, and number of AMD cases. Results Prevalence of early AMD increased from 3.5% (95% confidence interval [CI] 2.1%–5.0%) in those aged 55–59 years to 17.6% (95%

Deep submicron full-custom VLSI design of highly optimized high throughput low latency LDPC decoders

To satisfy the increasing demand for communication bandwidth more and more complex transmission systems are required. Channel coding as one fundamental block of such systems allows for a receiver-sided detection and correction of communication errors by introducing redundancy. Thereby, Low-Density Parity-Check (LDPC) codes achieve very low bit-error rates which are significantly lower than those of, for example, Turbo codes. Although, LDPC codes have already been introduced by R. G. Gallager in 1962, the complexity of LDPC decoders impeded their monolithic integration for a long time. The progress in VLSI-CMOS technology and the possibility to integrate digital circuits with millions of transistors allowed such an integration only in the recent years. Since then, LDPC codes have been adopted in various communication-system standards. Due to the complexity of the decoding algorithm, LDPC decoders highly impact the system features such as silicon area, throughput, latency, and energy requirements. Therefore, this thesis deals with the conception and design of area-, latency-, and energy-optimized LDPC decoders. For a systematic analysis of different decoder realizations, a new methodology has been developed which has a specified application as the starting point and derives efficient solutions. Therein, the optimization comprises all levels of CMOS design starting from the algorithmic system level and ending with the physical implementation level. As a first step, accurate area, timing, and energy cost models have been derived for two basic decoder architectures to allow for a quantitative analysis and optimizations on various design levels. In the following optimization, these models can be used to quantitatively compare different design strategies. For an analysis of possible fixed-point implementations of the algorithm, a parameterized HDL model has been developed. Based on this model, saturation and quantization effects on the decoding performance have been studied using hardware-accelerated simulations. A systematic analysis of the architecture design space results in a new area-, latency-, and energy-efficient architecture. To verify the efficiency of this new architecture, a LDPC decoder has been designed for an exemplary high-throughput application in a 40-nm CMOS technology. The features of this decoder are compared to the implementations known from literature. It could be shown that the joint optimization on all design levels enables a significant increase of the decoder efficiency in terms of area, throughout and energy by a factor of ten

Deep submicron full-custom VLSI design of highly optimized high throughput low latency LDPC decoders

To satisfy the increasing demand for communication bandwidth more and more complex transmission systems are required. Channel coding as one fundamental block of such systems allows for a receiver-sided detection and correction of communication errors by introducing redundancy. Thereby, Low-Density Parity-Check (LDPC) codes achieve very low bit-error rates which are significantly lower than those of, for example, Turbo codes. Although, LDPC codes have already been introduced by R. G. Gallager in 1962, the complexity of LDPC decoders impeded their monolithic integration for a long time. The progress in VLSI-CMOS technology and the possibility to integrate digital circuits with millions of transistors allowed such an integration only in the recent years. Since then, LDPC codes have been adopted in various communication-system standards. Due to the complexity of the decoding algorithm, LDPC decoders highly impact the system features such as silicon area, throughput, latency, and energy requirements. Therefore, this thesis deals with the conception and design of area-, latency-, and energy-optimized LDPC decoders. For a systematic analysis of different decoder realizations, a new methodology has been developed which has a specified application as the starting point and derives efficient solutions. Therein, the optimization comprises all levels of CMOS design starting from the algorithmic system level and ending with the physical implementation level. As a first step, accurate area, timing, and energy cost models have been derived for two basic decoder architectures to allow for a quantitative analysis and optimizations on various design levels. In the following optimization, these models can be used to quantitatively compare different design strategies. For an analysis of possible fixed-point implementations of the algorithm, a parameterized HDL model has been developed. Based on this model, saturation and quantization effects on the decoding performance have been studied using hardware-accelerated simulations. A systematic analysis of the architecture design space results in a new area-, latency-, and energy-efficient architecture. To verify the efficiency of this new architecture, a LDPC decoder has been designed for an exemplary high-throughput application in a 40-nm CMOS technology. The features of this decoder are compared to the implementations known from literature. It could be shown that the joint optimization on all design levels enables a significant increase of the decoder efficiency in terms of area, throughout and energy by a factor of ten